Kele’s Blog

Hi, I’m Kele. Welcome to my personal blog, a place to log some of my random thought. I try to write in English but still some content in Chinese. Current topics included here are:

FPGA Design

General

• Asynchronous Reset: the Misunderstanding, Problem and Solution

• FIFO

• SystemVerilog Variable and Net

Digital Signal Processing (DSP)

Generally target on Xilinx’s device. However, some parts should still suit for general design (e.g., Intel device and ASIC).

• Rounding

• DDS

• FIR

• Complex Multiplier

• Crest Factor Reduction I

Vivado

• Install Vivado on Ubuntu 20.04 LTS

• Write OOC DCP

• HSL

• SysGen

Zynq

• ZYNQ Easy Startup Guide, Part I

• ZYNQ Easy Startup Guide, Part II

Misc

• 8b/10b Encoding

• 12 Coins Game

About

• About Me and This Blog

© 2021 Kele, CC BY-NC-SA 4.0