SystemVerilog Variable and Net

2020-12-29

Verilog During school, my EDA teacher told me to use wire and reg in my Verilog design. And for a very long time, I have the feeling the wire is for model a logic connection and reg is for register. But that’s very wrong. The Verilog HDL LRM has defined many data types, and group them into two main groups: the net data types and variable data types. wire is most (and almost all) used net type, and reg is most used variable type.…

Create SD Image for Xilinx Qemu

2020-05-16

Along with PetaLinux, Xilinx provide a QEMU (Quick Emulator) for emulation Zynq/ZynqMP/MicroBlaze device on host PC. With QEMU, you can run Zynq programs, even a full Linux system without a real hardware. It’s very easy to interactive with it petalinux-boot --qemu. But how if we want to boot from SD card? …

Ubuntu Running on ZYNQ

2020-05-12

In my previous post ZYNQ Easy Startup Guide, Part II. We are have build a Linux image and run it on Pynq-Z2, using PetaLinux. There are different ways to get your Linux on Zynq running. Remember what components we need for a Zynq Linux system in ZYNQ Hard Startup Guide? PetaLinux generated image can be a good start point for us to start to replacing each components. This time we will try to run a Ubuntu RootFS on Zynq.…

Using Vivado Project With Git

2020-05-06

When working with my Vivado FPGA projects, I’m always seeking a way that get my project be tracked by a VCS (Version Control System), such as Git. It’s easy to get hdl files (*.vh, *.v, *.sv, *.hdl) working with it since they are plain text file. But it not true with other Vivado files. Xilinx has a application note XAPP1165 discussing this topic. Here is how I handle with it. …

Build ZYNQ Device Tree

2020-03-24

Let’s try build a boot image for ZYNQ, in a hard way. Part II will cover device tree. Device Tree is key component for running Linux. It’s often be called DTS (Device Tree Structure) or DTB (Device Tree Blob), different depend on whether it is source or compiled binary. We will try to build DTB from source. In fact, both u-boot and Linux need a DTS/DTB, we will talk it later.…

ZYNQ Hard Startup Guide

2020-02-29

There are different ways to get your Zynq running. Here is the components we need for a Zynq Linux system: .hdf or .xsa file, it includs FPGA design, Zynq chip configuration and peripherals information Cross-Compile Toolchain, also the C/C++ library associate with it. There are many to choose from: For PetaLinux/Yocto, it use generated toolchain when running build The toolchain ships with Vitis/Vivado installation Bootlin Buildroot generated Linaro (ARM) CodeSourcery … FSBL, first stage boot loader Usually build from Xilinx’s FSBL source.…

ZYNQ Easy Startup Guide, Part II

2020-02-27

In previous part I of ZYNQ Easy Startup Guide, I introduced how we start a bare metal PS program on ZYNQ7 board. In the second part of this serious, we will try to build and start Linux on ZYNQ, using Xilinx’s PetaLinux tool. …

ZYNQ Easy Startup Guide, Part I

2020-02-13

Xilinx release Vitis tool last year, replaces it’s old Xilinx SDK. There is few documents for it, and I’m planning to switch to it from SDK. Let’s try start from sketch so that we can study some basic concepts. Part I will including a simple PL design and a simple single core bare metal PS program, from project to boot on board. …

Xilinx Zynq Vip

2020-01-22

从 Vivado 2017.1 开始，Xilinx 的 Vivado 中集成了一个新的 IP，叫做 Zynq-7000 Verification IP（Zynq VIP）。这个 IP 主要用于 Zynq 处理器的逻辑仿真。根据 Xilinx 的说法，这个 IP 将会取代 Zynq-7000 BFM IP。Xilinx 有一个文档 DS940 来解释这个 IP 怎么用，不过并不是很清晰。我们来看看怎么用它。 …

Typora a Great Tool for Markdown

2020-01-21

Even Markdown sucks, it’s lightweight and good for writing blog and personal notes. Typora is Great tool for writing markdown. It provides standard markdown with some useful extensions, such as math and diagram. Some tips and tricks for Typora here. …